Validate at speed, not just at I/O

We pushed a small logic tweak on a case packer last week. I/O check passed, jog looked clean, and at 60 ppm it behaved. At 300 ppm the product eye chattered, the reject gate pulsed late, and we turned a minor change into a 40 minute jam clear and QA rework. The code was fine; our validation wasn't.

Now I treat every change with three tiers: static I/O prove-out, slow walk with real product, then a rate ramp to 110% for 10 minutes. I inject upsets: block the photoeye, simulate an encoder dropout, starve the infeed, E-stop mid cycle and recover. I trend timestamps on critical interlocks and record actual margins (eye detect to actuator fire). It adds 20 to 30 minutes, but it's cheaper than one pileup.

For those running legacy PLCs and high speed kit, what is your minimal validation set that reliably catches rate dependent failures? Any neat tricks to inject sensor noise or timing jitter on SLC/MicroLogix or old S7 without extra hardware?